The present invention relates to a method of dividing a wafer and a method of manufacturing a semiconductor device, and more particularly, to manufacturing steps of dicing semiconductor elements formed on a wafer into chips and sealing the chips in packages. These methods are suitably used in reducing semiconductor packages in size and thickness and adopted when a lager wafer is used.
The manufacturing steps for a semiconductor device are roughly classified into two: one is a step for forming patterns of various semiconductor elements on a wafer (semiconductor substrate) and the other is a step for dicing the semiconductor elements formed on the wafer into chips and sealing them in packages. Recently,, to reduce manufacturing cost of semiconductor devices, the diameters of wafers have been increased. At the same time, to enhance the packaging density, the packages are desired to be miniaturized (decreased in size and thickness).
Conventionally, in order to seal a semiconductor chip in the miniaturized package, a wafer is reduced in thickness prior to dicing the wafer into chips. More specifically, a bottom surface of a wafer (opposite to a pattern formation surface (major surface) of the wafer) is lapped by a grindstone and polished by free grind grains, and thereafter the wafer is diced. When the wafer is lapped, the pattern formation surface of the wafer is protected by attaching an adhesive sheet thereon or coated with a resist. Thereafter, grooves are formed along dicing lines formed on the major surface of the wafer. These grooves are formed by means of a diamond scriber, a diamond blade, a laser scriber, or the like. In the dicing step, a half-cut method in which the wafer itself is diced to xc2xd of the thickness of the wafer or diced until the wafer is about 30 xcexcm thick; a half-cut method in which an adhesive sheet is attached to the bottom surface of the wafer, and thereafter, the wafer is diced in the same manner as above; or a full-cut method in which the wafer with the adhesive sheet attached thereto is completely diced until the adhesive sheet is cut into to a depth of 20 to 30 xcexcm. The half-cut method requires a chip-separation step. When the wafer is used alone, the wafer is separated into chips by sandwiching it between soft films and applying an external force to the wafer by means of a roller or the like. When the adhesive sheet is attached to the wafer, the wafer is separated into chips by applying an external force to the wafer via the sheet. The chips thus separated are removed from the sheet in the following manner. The bottom surface of the sheet is pushed up by a pickup needle provided in a die bonding device. The needle penetrates the sheet and comes in direct contact with the bottom surface of each chip and further lifts up the chip to remove it from the sheet. The surface of the chip thus removed is adsorbed by means of a tool called a xe2x80x9ccolletxe2x80x9d and mounted on an island of a lead frame. After each of the pads of the chip is electrically connected to an inner lead portion of the lead frame by means of wire bonding, the resultant chip is sealed in a package. The chip is mounted on the island by previously applying a conductive paste on the island, by using gold-silicon eutectic, or by a method in which a thin metal film is deposited on the bottom surface of the wafer and then the wafer is mounted by use of solder.
FIGS. 1 to 7 are used for explaining an example of the conventional wafer dividing method and semiconductor device manufacturing method mentioned above. More specifically, FIG. 1 illustrates a step of attaching a surface protection tape on a wafer; FIG. 2 is a step of lapping and polishing the bottom surface of the wafer; FIG. 3 is a step of removing the surface protection tape; FIGS. 4A and 4B are steps of fixing the wafer on a fixing sheet; FIG. 5 is a step of dicing the wafer; FIG. 6 is a step of picking up separated chips; and FIG. 7 is a die bonding step.
As is shown in FIG. 1, after an element formation step is completed, the bottom surface of a wafer 1 is fixed on a porous chuck table 2. A protection tape 3 is attached to a pattern formation surface 1xe2x80x2 of the wafer 1 by moving an attachment roller 4 in the direction indicated by an arrow in the figure while rotating it. Subsequently, as shown in FIG. 2, the wafer 1 is fixed on a chuck table 5 with the pattern formation surface 1xe2x80x2 thereof (having the protection tape 3 attached thereto) faced down. The bottom surface of the wafer 1 is lapped and polished to a predetermined depth (i.e. a predetermined thickness of a finished chip) by means of a grindstone 6. Thereafter, as shown in FIG. 3, a tape 7 (for use in removing the protection tape 3) is attached to the protection tape 3 and then the protection tape 3 is removed from the pattern formation surface 1xe2x80x2. Subsequently, a flat ring 8 is fixed on a wafer fixing sheet 9, as shown in FIG. 4A, to prevent the sheet 9 from becoming slack or wrinkled. In this state, the wafer 1 is fixed on the sheet 9 within the opening of the flat ring 8, as shown in FIG. 4B. The sheet 9 having the wafer 1 fixed thereon and the flat ring 8 are fixed on a dicing chuck table 10. The wafer 1 is diced (full-cut) by a dicing blade 11 into chips 12 (see FIG. 5). Thereafter, as is shown in FIG. 6, a pickup needle 13 is allowed to pass through the sheet 9 from the bottom thereof and brought in contact with the bottom surface of each chip 12. The chip 12 is pushed upward by the needle 13 to thereby remove it from the sheet 9. The separated chip 12 is mounted on an island 14 of a lead frame, as shown in FIG. 7, by using a die bonding adhesive 15 such as a conductive paste. Thereafter, inner lead portions (not shown) of the lead frame are wire-bonded to pads of the chip 12, and the resultant structure is sealed into a package formed of a resin or ceramic. In this way, the semiconductor device are completely fabricated.
However, the above-described wafer dividing method and semiconductor device manufacturing method have the following problems (a) to (c).
(a) The wafer is easily broken while it is reduced in thickness by lapping. Even if the wafer is lapped with the protection tape being attached thereto, the wafer may warp by distortion due to the lapping. As a result, the wafer may be caught and broken during transfer within the lapping apparatus. The wafer is reduced in strength as the wafer becomes thin or large in diameter. Therefore, in the transfer method presently employed of transferring the wafer after it is reduced in thickness in order to apply various treatments, there is a high possibility of breaking the wafer. For example, the durable stress of the wafer is up to about 1.6 Kgf/mm2 in the case of a wafer having a thickness of 400 xcexcm, whereas, when the thickness of the wafer is reduced to 200 xcexcm, the durable stress decreases to xc2xc as low as 0.4 Kgf/mm2.
(b) Since two sheets are used for protecting the pattern formation surface and for holding the wafer at the time of dicing, cost for materials increases. Extra steps are required for attaching and removing each of the two sheets, so that the number of manufacturing steps also increases.
(c) When the wafer is diced, the bottom surface of the wafer is chipped more than the upper surface side, with the result that the breaking-resistance of the chip decreases. In addition, recently transistors, resistors and capacitors for monitoring various characteristics (hereinafter referred to as xe2x80x9cTEGxe2x80x9d (Test Element Group)) have been arranged on dicing lines to integrate devices with a high density, although they are arranged within the chip in conventional devices. Since the TEG devices are formed of oxide films, aluminum, etc., when the TEG devices are diced by using a diamond blade, the clogging of the blade easily occurs. As a result, the cutting edge of the blade is made dull. Therefore, when the TEG is arranged on the dicing lines, the chipping of the bottom side of the wafer further increases. Since the semiconductor substrate is generally formed of a fragile material such as silicon or GaAs, if there is a crack, the breaking resistance of the wafer is easily decreased.
To solve the aforementioned problems, the semiconductor device manufacturing method disclosed in Japanese Patent Publication No. 2737859 suggests that the upper surface (pattern formation side) of the wafer is cut to a predetermined depth, the wafer (the surface pattern formation side) and a fitting tool are adhered on a base film, and the bottom surface of the wafer is polished to divide into chips.
However, in the method (No. 2737859), when the chips are removed from the base film, each of the chips is removed by pushing up through the bottom surface by a lift-up tool. At this time, the base film is distorted. Since the base film is adhered to the element formation surface (pattern formation surface) of the wafer, the element formation surface is inevitably lifted up by the lift-up tool. Therefore, the semiconductor elements may be damaged.
To prevent the semiconductor device from being damaged by the lift-up tool, for example, Japanese Patent Application KOKAI Publication No. 5-74934 suggests a method in which a die-bonding tape is attached to the bottom surface of the wafer after the wafer is divided into chips by lapping the bottom surface, and thereafter an adhesive sheet (base film) is removed.
However, this method (No. 5-74934) produces another problem. Since the chips are held by the die-bonding tape alone, the chips cannot be held flat. As a result, the chips interfere with each other and get chipped when they are transferred. In this way, there is a problem of quality degradation is produced.
In brief, the conventional wafer dividing method and semiconductor device manufacturing method have the following problems mentioned above. First, the wafer is easily broken when the wafer is reduced in thickness or transferred. Second, pieces chipped off from the bottom side of the wafer are larger than the surface side when the wafer is diced. As a result, the breaking resistance of the chip decreases.
To overcome these problems, a method has been suggested in which a notch is made in the element formation surface of the wafer followed by lapping the bottom surface to divide the wafer into chips. However, this method has a problem. The semiconductor elements are damaged when the chips are picked up. In addition, when transferred, the chips mutually interfere with each other and chipping occurs. Therefore, a problem of quality degradation is accompanied.
A first object of the present invention is to provide a method of dividing a wafer while preventing the wafer from being broken and chipped when the wafer is reduced in thickness by lapping or is transferred.
A second object of the invention is to provide a method of dividing a wafer capable of improving the quality and manufacturing yield of chips.
A third object of the invention is to provide a method of manufacturing a semiconductor device while preventing a wafer from being broken and chipped when the wafer is reduced in thickness by lapping or is transferred, thereby preventing quality degradation of the wafer.
A fourth object of the invention is to provide a method of manufacturing a semiconductor device capable of improving the quality and manufacturing yield of the semiconductor device.
The first and second objects can be achieved by a wafer dividing method comprising:
a first step of forming grooves in an element formation surface of a wafer, along dicing lines or chip dividing lines, the grooves being deeper than a thickness of a finished chip;
a second step of attaching a holding member on the element formation surface of the wafer;
a third step of lapping and polishing a bottom surface of the wafer to the thickness of the finished chip, thereby dividing the wafer into chips; and
a fourth step of transferring the chips while holding the chips by porous adsorption.
According to the wafer dividing method mentioned above, a wafer is divided into chips by forming grooves deeper than a thickness of a finished chip in an element formation surface of a wafer, and lapping and polishing a bottom surface of the wafer to the thickness of the finished chip. It is therefore possible to prevent breakage and chipping of the wafer. In addition, the chips divided in the above are transferred while holding them by porous adsorption. It is therefore possible to prevent mutual interference between the chips, preventing occurrence of the chipping. As a result, quality degradation of the chips is successfully prevented, so that the chips can be manufactured in a high quality and in a high yield.
The first object of the present invention can also be achieved by a wafer dividing method comprising:
a first step of forming grooves in an element formation surface of a wafer along dicing lines or chip dividing lines, the grooves being deeper than a thickness of a finished chip;
a second step of attaching a first holding member on the element formation surface of the wafer;
a third step of lapping and polishing a bottom surface of the wafer to the thickness of the finished chip, thereby dividing the wafer into chips;
a fourth step of transferring the chips while holding the chips by porous adsorption;
a fifth step of attaching bottom surfaces of the chips to a second holding member having a flat ring; and
a sixth step of removing the first holding member.
According to the wafer dividing method mentioned above, a wafer is divided into chips by forming grooves deeper than a thickness of a finished chip in an element formation surface of a wafer and lapping and polishing a bottom surface of the wafer to the thickness of the finished chip. It is therefore possible to prevent the wafer from being broken and chipped. Furthermore, the chips are transferred while holding them by porous adsorption. It is therefore possible to prevent mutual interference between the chips, preventing occurrence of chipping. Moreover, the first holding member is removed by attaching the bottom surfaces of the chips to the second holding members having a flat ring. It is therefore possible to prevent the semiconductor elements from being damaged when they are picked up. In addition, since the chips can be held flat by the flat ring, it is possible to prevent mutual interference between the chips, preventing occurrence of chipping. Therefore, quality degradation of the formed chips is prevented to form high--quality chips with a high yield.
The third and fourth objects of the present invention can also be achieved by a semiconductor device manufacturing method comprising:
a first step of forming semiconductor elements on a major surface of a wafer;
a second step of forming grooves in the major surface of the wafer along dicing lines or chip dividing lines, the grooves being deeper than a thickness of a finished chip;
a third step of attaching a holding member on the major surface of the wafer;
a fourth step of lapping and polishing a bottom surface of the wafer to the thickness of the finished chip, thereby dividing the wafer into chips;
a fifth step of transferring the chips while holding the chips by porous adsorption; and
a sixth step of mounting the chips transferred on lead frames and sealed in packages.
According to the semiconductor device manufacturing method mentioned above, a wafer is divided into chips by forming grooves deeper than a thickness of a finished chip in an element formation surface of a wafer, and lapping and polishing a bottom surface of the wafer to the thickness of the finished chip. It is therefore possible to prevent breakage and chipping of the wafer. Furthermore, the chips are transferred to a die-bonding step while being held by porous adsorption. It is therefore possible to prevent mutual interference between the chips, preventing occurrence of the chipping. As a result, the quality and yield of the chips can be improved.
Furthermore, the third and fourth objects of the present invention can be achieved by a semiconductor device manufacturing method comprising:
a first step of forming semiconductor elements on a major surface of a wafer;
a second step of forming grooves in the major surface of a wafer along dicing lines or chip dividing lines, the grooves being deeper than a thickness of a finished chip;
a third step of attaching a first holding member on the major surface of the wafer;
a fourth step of lapping and polishing a bottom surface of the wafer to the thickness of the finished chip, thereby dividing the wafer into chips;
a fifth step of transferring the chips while holding the chips by porous adsorption; and
a sixth step of attaching bottom surfaces of the chips to a second holding member having a flat ring;
a seventh step of removing the first holding member; and
an eighth step of mounting the chips on lead frames and sealed in packages.
According to the semiconductor device manufacturing method mentioned above, a wafer is divided into chips by forming grooves deeper than a thickness of a finished chip in the surface of a wafer on which surface semiconductor elements are formed, and lapping and polishing a bottom surface of the wafer to the thickness of the finished chip. It is therefore possible to prevent breakage and chipping of the wafer. Furthermore, the chips are transferred while being held by porous adsorption. It is therefore possible to prevent mutual interference between the chips, preventing occurrence of the chipping. Furthermore, since the first holding member is removed by attaching the bottom surfaces of the chips to the second holding member having a flat ring, it is possible to prevent the semiconductor elements from being damaged when the chips are picked up in order to mount them on the lead frame. In addition, since the chips can be held flat by the flat ring, it is possible to prevent mutual interference between the chips, preventing occurrence of the chipping during transfer. As a result, the quality and yield of the chips can be improved.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.